The present invention is generally related to semiconductor memories and data storage and, more particularly, to an image memory chip and a method for storing image data.
Presently, synchronous dynamic random access memories (SDRAM) with a large bandwidth have come to the forefront as a leading type of memory. More specifically, the data volume per pixel has increased manifold since multiple-color images and three-dimensional images have become more common in image memories. Thus, for many applications, SDRAMs are now the preferred vehicle to process high volumes of data at high speed.
In order to facilitate the understanding of the invention and put it in the proper perspective, a conventional dynamic random access memory (DRAM) will first be considered for comparison purposes. In DRAMs, the read and write accesses to a cell are executed by specifying a row address (word line) and a column address (bit line) of the memory cells that are typically arranged in a matrix formation. When the row address of a target memory cell is specified, data on the word line related to the designated address is latched to sense amplifiers. When the column address is specified, data in the column address is selected from that already latched into the sense amplifiers and transferred to the output drivers. Since data of the designated row address is coupled to sense amplifiers, only data on the same word line can be continuously read by specifying the column addresses. In a page mode, wherein data of the same row address is continuously addressed, there is no need to respecify the row address in order to achieve a high speed data access.
In a synchronous DRAM (hereinafter referred to as SDRAM), when the row and column addresses of a first data are specified, any addresses that follow are automatically generated within the memory chip such that the data appearing at the output drivers is continuously in synchronization with the clock. Burst lengths of 2, 4, 8, and 16 can be selected as the most suited data rate for a continuous transmission. In burst mode, wherein data is accessed in synchronization with the clock, data is read at every clock cycle. Thus, a faster access may be achieved than the previously described page mode.
The burst mode of the SDRAM is essentially the same as the conventional page mode, except that the data is accessed in synchronization with the clock signal. Accordingly, a faster access can be achieved by selecting only the first column address from a number of sense amplifiers activated by the single row address. Thus, when the same row address is specified, a fast read operation is obtained. However, when a different row address is designated, the reading speed is drastically reduced because new data must be latched to the sense amplifiers.
In order to improve the access speed for different row addresses, an SDRAM typically is structured in a plurality of memory banks operating separately from each other. For example, while one bank is being accessed, another bank can be activated or precharged in order not to delay the data transmission.
FIG. 12 shows an example of a typical memory chip organization in a SDRAM. Memory chip 90 consists of four banks, common data I/Os (inputs/outputs), and common address inputs. By way of example, memory chip 90 is a 64 Mb chip (2 Mb) with 32 I/Os. Twenty-one address lines are required to specify one of 2 M (=221) addresses. In many instances, for a time-shared row and column addressing arrangement, half the number of address lines (i.e., 11) is required to specify the 2 M addresses. When inputting an address, data can be read or written via the 32 I/O terminals.
In image display memory devices, a display screen is scanned from top to bottom on a line-by-line basis. Accordingly, pixels aligned in a horizontal line are mapped into memory in such a manner that a faster access to the pixel data can be achieved. More specifically, as shown in FIG. 13(a), pixel data aligned in a horizontal line is mapped into memory such that it can be stored in the same word line (i.e., the same row address). Memory mapping makes it possible to read at high speed the pixel data that is aligned in a row in the scanning direction.
FIG. 13(b) is a detailed memory map diagram of the pixel""s data. In this figure, there is shown in graphic image 92, PIX (m, n), a pixel in the mth row from the top and the nth column from the left end, where m and n are integers ranging from 0 to 3. Four pixels aligned in the top horizontal line are stored in the same word line of bank 0. Similarly, four pixels aligned in the second, third, and fourth horizontal lines from the top are stored in the same word lines of bank 1, bank 2 and bank 3, respectively. If the pixel consists of 64 bits, the pixel""s data can be read in a 2-bit burst operation (since the number of I/O terminals is 32).
FIG. 14 is a schematic block diagram showing the interconnections linking four groups of 8 I/Os and four banks 0, 1, 2, and 3. FIG. 15(a) shows the memory mapping as it relates to the four groups of 8 I/Os and the four banks. Each block labeled S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14 and S15 indicates an 8-bit burst of data. S0, S4, S8 and S12 represent the data in bank 0; S1, S5, S9 and S13, data in bank 1; S2, S6, S10 and S14 data in bank 2; and S3, S7, S11 and S15, data in bank 3. When data of the four pixels in the top horizontal line is read, pixel PIX(0, 0) is extracted from the first and second bits of 8-bit burst of data S0, S4, S8, and S12 in bank 0, as shown in FIG. 15(b). In the same manner, pixels PIX(0, 1), PIX(0, 2), and PIX(0, 3) are obtained from the third and fourth bits, the fifth and sixth bits, and the seventh and eighth bits, respectively. In this manner, when data of four horizontal pixels is read, an 8-bit burst length is selected to read data from each bank. When data of four pixels arranged in a 2 by 2 formation is read, a 4-bit burst length is selected to read data from two banks. For example, when data in the four pixels located in the upper left corner of FIG. 15(c) is read, pixels PIX(0, 0) and PIX(0, 1) are obtained from the 4-bit burst data of S0, S4, S8, and S12 in bank 0. In the same manner, pixels PIX(1, 0) and PIX(1, 1) are obtained from the 4-bit burst data S1, S5, S9, and S13 in bank 1. When data of four vertical pixels is read, a 2-bit burst length is selected to read data from four banks.
To change the burst length, the memory chip must be in standby mode to successfully suspend the data transmission. In order to resume the data transmission, a word line needs to be reactivated. Thus, changing the burst length lowers the data rate. When data in the pixels in a vertical line or in a diagonal line is accessed, the access speed becomes slower than that of accessing data of a horizontal pixel line. When a plurality of banks is accessed, power consumption increases significantly because the word lines of each bank are activated. For example, to access a horizontal pixel line, only one bank needs to be accessible. On the other hand, in order to access a vertical pixel line, four banks are required, in which case, the power consumption increases fourfold. A multiple bank structure complicates the design of the memory and increases the production cost. Furthermore, as shown in FIG. 14, it further requires extended wiring and complex interconnections between the banks and the I/O terminals.
Objects of the Invention
It is an object of the present invention to provide a memory chip having fast access to pixel data for graphic image stored in the memory.
It is a further object to provide a method for storing image data for graphic imaging.
In a first aspect of the invention, there is provided a memory chip that includes data input/output terminals (I/Os) divided into a plurality of blocks; memory arrays divided into the same number of blocks as the data I/Os to store data received from or sent to respective data I/Os; and means for specifying addresses for writing data received from data I/Os and for reading data sent to data I/Os in each block. In such a memory chip, the means for specifying addresses specifies an address in each block of memory arrays and the specified data can be sent to each data I/O. In a like manner, data received from each data I/O can be stored in the specified address of each block.
In a second aspect of the invention, there is provided a method for storing data storage that includes the steps of: specifying a write address of data received from data I/Os divided into a plurality of blocks; and writing data received from each data I/O into each specified address of the memory arrays.
The memory chip and the method for storing data according to the present invention make it possible to read data in a vertical line, in a diagonal line, and the like at the same access speed as reading data in a horizontal line. In addition, the power consumption of the chip is significantly reduced, and the wiring arrangement of the I/Os is greatly simplified.